Job Description

Company:

Qualcomm Technologies, Inc.

Job Area:

Engineering Group, Engineering Group > Analog Mixed Signal Design

General Summary:

QCT mixed-signal IP design team is looking for talented analog integrated circuit designers at various levels to help with designing high-speed, high-performance and low-power mixed-signal IPs (SerDes, DDR, PLL, DAC, ADC, sensors, etc.) for Qualcomms products targeted for 5G, AI/ML, compute, and automotive applications. QCT mixed-signal design team consists of architects and ASIC designers, protocol experts, signal processing engineers, and algorithm designers and we are looking for new talents in the area of analog circuit design for our ASICs.

Responsibilities:

1. Work in our analog design team for schematic capture and simulations and participate in architecture definition and analog/digital design partitioning.
2. Schematic capture and simulations in the Cadence Virtuoso tool suite.
3. Work with cross functional teams (i.e. layout and digital teams).
4. Work with testing team for silicon bringup and debugging.

Required for this Role:

1. Master's degree in Electrical Engineering or related field.
2. Demonstrated interest in analog circuit design by course selections and/or work experience.
3. Experience working with ASIC design tools such as Cadence Virtuoso.

Preferred Qualifications:

1. Several years of industry experience in the area of analog integrated circuit/system design.
2. Experience as a high-speed analog designer of mixed-signal IPs, such as CTLE, CDR, PLL RXAFE, PLL, DAC, ADC.
3. Familiar with Matlab and Python and good understanding of architecture, system and integration aspects for mixed-signal.
4. Good understanding of design for yield and production challenges with high-speed serial links.
5. Good understanding of Signals and Systems, Sampled Domain signal processing a plus.

Minimum Qualifications:

1. Bachelor's Degree in Electrical Engineering with 2+ years of experience with analog or mixed-signal integrated circuit design in nanometer planar CMOS or FinFET and 4+ years of ASIC design, verification, or related work experience.
2. OR Master's degree in Electrical Engineering or related field and 4+ years of ASIC design, verification, or related work experience.
3. OR PhD in Electrical Engineering or related field and 2+ of years ASIC design, verification, or related work experience.
4. 2+ years of experience using one or more design tools (e.g., CADENCE, SPICE, MATLAB, and/or Verilog/VHDL).

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